TABLE 1ATPG results for single stuck-at faults and LOC delay testingdetails of the circuitsstuck-at teststransition testcircuitsPIsPOsFFsgatesvecFCMAXCPU(s)vecFCMAXCPU(s)b1924306,642225,800154698.8036593560965284.47405311246ethernet9411513,715105,37190699.2019311480350199.3921597616vga_lcd8710917,079153,66498099.4058842940904599.64603214110netcard1564697,796568,986226099.10737146802781097.52960935220
Test data volume for LOC transition fault testing is far more than that of single stuck-at testing. Table I presents test generation results for LOC transition fault testing and single stuck-at fault testing. The columns with vec, FC and MAX represent the number of tests, fault coverage, and the number of maximum care bits for the whole test set, respectively. It is found that the number of test vectors for LOC transition fault testing is far more. The maximum number of care bits for single stuck-at tests is also apparently less than that for LOC transition fault testing. It is important for us to present an effective method for LOC transition fault test compression. Scan chain designs are used for both single stuck-at fault testing and LOC transition fault testing.
The current commercial EDA tools cannot handle test compression for LOC delay testing well. Excessive test power dissipation of test power has been a severe problem, which is even more difficult to handle for LOC delay testing. The huge amount of test data for delay testing makes test compression for delay testing even more important than that for stuck-at fault testing. Test application of compressed test data produces further more test power. Therefore, there is a strong need for an effective low-power test compression approach.
In this invention, we propose a new low-power test compression architecture for LOC-based transition fault testing. We present the major contributions of this invention as follows: (1) the LFSR established by the selected primitive polynomial and the selected number of extra variables injected to the LFSR; (2) the scan tree architecture for LOC transition fault testing; and (3) the new gating technique. (4) A new static test compaction scheme is proposed by bitwise modifying the values of a seed and the extra variables. (5) A new technique for test point insertion is proposed for LOC delay testing in the two-frame-circuit model, which apparently reduces test data volume.
Most of the previous deterministic BIST approaches did not include low-power concerns. We intend to present a new method that effectively combines an efficient low-power test application scheme for LOC delay testing. Power consumption for delay testing is an even more difficult problem because of a much larger number of delay test patterns. We propose a low-power test compression approach for LOC transition fault testing by using new a DFT architecture, test application scheme, seed modification and test point insertion technique.
As for the DFT architecture, our method introduces a new primitive polynomial selection method, and a new scheme to select the number of extra variables. Using the proposed DFT architecture, all deterministic test pairs can be encoded into a seed with a sequence of extra variables injected into the LFSR.
Test point are inserted into the circuit by reducing the potential care bits for each deterministic test pairs. This is implemented by using a cost function for LOC transition fault testing. Extra pins of the control points are connected to the PPIs or PIs in the two-frame circuit model by circuit structural analysis.
In order to further reduce test data volume, we propose a new seed modification technique. The seed modification technique can remove some seeds by revising the calculated values of the extra variables and the seed for each test pair. The seed modification technique is implemented by complementing value of each bit for the seed and extra variables, which removes some seeds and reduces test data volume without any additional control data. A new test point insertion placement scheme is proposed to compress test data volume based on the influence-cone based testability measure for LOC transition fault testing. Test point insertion is to reduce the number of care bits to detect faults. The extra pin of a control test point is connected to a pseudo-primary input (PPI). Extra pins of multiple control test points can share the same PPI. The pin overhead can be well-controlled based on the above scheme.